1. Technical Field of the Invention
The present invention relates generally to negative charge pump circuits and, more particularly, to a current protection scheme for use with such negative charge pump circuits.
2. Description of Related Art
Reference is made to FIG. 1 which shows a circuit diagram for a prior art negative charge pump circuit. An oscillator 10 generates an oscillating reference clock signal which is applied to a non-overlap signal generator 12 outputting a first clock signal 14 and a complementary second clock signal 16. The first and second clock signals 14 and 16 are received by a level shifter 18 which outputs four control signals (C1-C4) 20, 22, 24 and 26 that are applied to the gates of four MOS power transistors 30, 32, 34 and 36, respectively.
The first MOS power transistor 30 is of the PMOS type having its source terminal coupled to a reference voltage (Vdd). The gate of the first MOS transistor 30 receives the first control signal (C1) 20. The second MOS power transistor 32 is of the NMOS type having its source terminal coupled to a ground reference voltage. The gate of the second MOS transistor 32 receives the second control signal (C2) 22. The drains of the first and second MOS transistors 30 and 32 are coupled together and to the first terminal of a first capacitor 40 (referred to as the fly capacitor).
The third MOS power transistor 34 is of the NMOS type having its source terminal coupled to the ground reference voltage. The gate of the third MOS transistor 34 receives the third control signal (C3) 24. The fourth MOS power transistor 36 is of the NMOS type having its source terminal coupled to a negative voltage (Vneg) output 42. The gate of the fourth MOS transistor 36 receives the fourth control signal (C4) 26. The drains of the third and fourth MOS transistors 34 and 36 are coupled together and to the second terminal of the first (fly) capacitor 40.
An output (or load) capacitor 46 is coupled between the negative voltage (Vneg) output 42 and the ground reference voltage.
Reference is now made to FIG. 2 which shows a timing diagram illustrating the control signals for operating the charge pump circuit of FIG. 1. During a first phase of operation 70, the first (C1) and third (C3) control signals 20 and 24 turn on the first and third power transistors 30 and 34. This charges the fly capacitor 40 towards the reference voltage Vdd. In this first phase of operation, the first (C1) control signal 20 is low and the third (C3) control signal 24 is high. The second (C2) and fourth (C4) control signals 22 and 26 are both low (thus shutting off the second and fourth transistors 32 and 36).
During a second phase of operation 72, the second (C2) and fourth (C4) control signals 22 and 26 turn on the second and fourth power transistors 32 and 36. This charges the load capacitor 46 (with the positive side of the fly capacitor 40 being connected the ground reference side of the load capacitor 46), thus producing a negative voltage Vneg at the output 42. In this second phase of operation, the second (C2) control signal 22 is high and the fourth (C4) control signal 26 is high. The first (C1) and third (C3) control signals 20 and 24 are high and low, respectively, (thus shutting off the first and third transistors 30 and 34).
It will be recognized that the control signals C1, C2 and C4 have a same phase relationship and thus may be generated from the first clock signal 14, while the control signal C3 has an opposite phase relationship and thus may be generated from the complementary second clock signal 16. The level shifter 18 applies any necessary level shifting (not explicitly shown in FIG. 2) so that the gate voltages are set so as to fully turn on and fully turn off the power transistors 30, 32, 34 and 36 during circuit operation.
The first and second phases are continuously repeated to pump the output 42 voltage Vneg towards the desired negative reference voltage (−Vdd). Before the output 42 reaches its desired final voltage state (i.e., before Vneg reaches −Vdd), high currents may be experienced in both the first and second transistors 30 and 32 when either is turned on during pumping. For example, a high current may exist in first transistor 30 when charging the fly capacitor 40 during the first phase of operation (C1 low), and a high current may exist in second transistor 32 when charging the load capacitor 46 during the second phase of operation (C3 high). There is a need to provide current protection to the first and second transistors 30 and 32.